Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm-Reference-Cited by-同舟云学术

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Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm

Published:2018-12 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
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Author:

Samudrala Harsha Keerthan,Qadeer Shaik,Azeemuddin Syed,Khan Zafar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8716489/8719323/08719380.pdf?arnumber=8719380

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Spectrum Processing Chiplet Based on FFT Algorithm;Micromachines;2023-02-07

2. Design and Implementation of a Real-time Parallel FFT for a Direction-Finding System on an FPGA;2022 IEEE High Performance Extreme Computing Conference (HPEC);2022-09-19

3. Computation-Efficient and Multiplierless Hardware Realization of Decimation in Time FFT;2022 IEEE Region 10 Symposium (TENSYMP);2022-07-01

4. A Trusted Distributed Routing Scheme for Wireless Sensor Networks Using Block Chain and Jelly Fish Search Optimizer Based Deep Generative Adversarial Neural Network (Deep-GANN) Technique;Wireless Personal Communications;2022-06-10

5. STQCA-FFT: A fast fourier transform architecture using stack-type QCA approach with power and delay reduction;Journal of Computational Science;2022-04

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