Author:
Barve Sampada,Raveendran Sithara,Korde Charudatta,Panigrahi Trilochan,Nithin Kumar Y.B.,Vasantha M.H.
Cited by
5 articles.
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1. Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning;Machine Learning for VLSI Chip Design;2023-06-23
2. Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms;Journal of The Institution of Engineers (India): Series B;2023-01-06
3. Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA;2021 International Conference on Electrical, Computer and Energy Technologies (ICECET);2021-12-09
4. High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA;International Journal of Circuit Theory and Applications;2021-08-26
5. Design and Comparison of Multiplier using Vedic Sutras;2019 5th International Conference On Computing, Communication, Control And Automation (ICCUBEA);2019-09