Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

Author:

Ananthalakshmi A.V.,Divyaparameswari P.,Kanimozhi P.

Publisher

Wiley

Reference23 articles.

1. Vedic-Based Squarers with High Performance

2. Performance Evaluation of Squaring Operation by Vedic Mathematics

3. An Improved Squaring Circuit for Binary Numbers

4. Kumar A.;Kumar D.;Hardware implementation of 16 * 16 bit multiplier and square using Vedic mathematics.International Conference on Signal Image and Video Processing (ICSIVP)2012 309‐314.

5. Design of high speed Vedic square by using Vedic multiplication techniques;Kumar G. G.;International Journal of Scientific & Engineering Research,2013

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