Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs-Reference-Cited by-同舟云学术

Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs

Published:2022-10-03 Issue: Volume: Page:
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Container-title:2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT)
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Author:

Sai Kumar Aruru¹,Deekshana M.¹,Bharath Sreenivasulu V.²,Prasad Somineni Rajendra¹,Kanthi Sudha D.¹

Affiliation:

1. VNR Vignana Jyothi Institute of Engineering and Technology,Department of ECE,Hyderabad,India

2. Vellore institute of technology,Department of SENSE,Chennai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9984157/9984211/09984269.pdf?arnumber=9984269

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