1. FIVE STAGE PIPELINED MIPS PROCESSOR VERIFICATION SEQUENCE MODULE USING UVM;2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI);2023-04-19
2. Cost Effective Network Flow Measurement for Software Defined Networks: A Distributed Controller Scenario;IEEE Access;2018
3. FPGA Implementation of Low Power Pipelined 32-Bit RISC Processor Using Clock Gating;Proceedings of the International Conference on Data Engineering and Communication Technology;2016-08-25
4. DESIGN OF RISC PROCESSOR USING VHDL;International Journal of Research -GRANTHAALAYAH;2016-06-30
5. Design of RISC Based MIPS Architecture with VLSI Approach;Wireless Networks and Computational Intelligence;2012