Single event transient analysis of isolation problems for the high side devices in a 0.18μm BCD Process
Author:
Affiliation:
1. Wuxi Microelectronics Research Institute,Wuxi,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10389810/10390725/10390892.pdf?arnumber=10390892
Reference7 articles.
1. BCD (Bipolar-CMOS-DMOS) technology trends for power management IC
2. Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-μm BCD Process;Nidhi
3. Smart power IC simulation of substrate coupled current due to majority and minority carriers transports
4. High-Side nLDMOS Design for Ensuring Breakdown Voltages Over 100 V
5. Robustness Enhancement of the Floating NBL BCD Architecture: Parasitics Suppression and Addition of Partially Isolated Diode for Localized Voltage Control
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