Organic Interposers Using Zero-Misalignment-Via Technology and Silicon Wafer Carriers for Large Area Wafer-Level Package Applications
Author:
Affiliation:
1. Intel Corp.,Chandler,AZ,USA
2. Intel Corp.,Hillsboro,OR,USA
3. Intel Corp.,Aloha,OR,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10564841/10564831/10564920.pdf?arnumber=10564920
Reference14 articles.
1. Supercarrier Redistribution Layers to Realize Ultra Large 2.5D Wafer Scale Packaging by CoWoS
2. CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package
3. FO-EB-T Package Solution for High Performance Computing
4. Novel 2.5D RDL Interposer Packaging: A Key Enabler for the New Era of Heterogenous Chip Integration
5. A unified yield model incorporating both defect and parametric effects
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Zero-misalignment Technology Achieves 333 IO/mm/layer on Mold;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
2. IR Laser Debond From Silicon Carrier Wafers With Inorganic Thin Film Release Layers for High-Density 2.5D and 3D Integration;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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