Process Flow Modelling and Characterisation of Stacked Gate-All-Around Nanosheet Transistors-Reference-Cited by-同舟云学术

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Process Flow Modelling and Characterisation of Stacked Gate-All-Around Nanosheet Transistors

Published:2022-07-04 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 22nd International Conference on Nanotechnology (NANO)
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Author:

Mumba K.¹,Cai S.¹,Kalna K.²

Affiliation:

1. Swansea University Bay Campus,Faculty of Science & Engineering,Department of Electronic & Electrical Engineering,Swansea,Wales,United Kingdom,SA1 8EN

2. Nanoelectronic Devices Computational Group, Swansea University Bay Campus,Faculty of Science & Engineering,Swansea,Wales,United Kingdom,SA1 8EN

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9928528/9928587/09928725.pdf?arnumber=9928725

Reference18 articles.

1. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

2. 3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors

3. Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes;IEEE Journal of the Electron Devices Society;2024

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