A FinFET Design for Superior High-Voltage Performance
Author:
Affiliation:
1. Pohang University of Science and Technology (POSTECH),Department of Electrical Engineering,Pohang,South Korea,37673
2. Pohang University of Science and Technology (POSTECH),Department of Convergence IT Engineering,Pohang,South Korea,37673
Funder
IDEC
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9928528/9928587/09928741.pdf?arnumber=9928741
Reference13 articles.
1. Zener and avalanche breakdown in As-implanted low-voltage Si n-p junctions
2. High-Voltage Drain-Extended FinFET With a High-${k}$ Dielectric Field Plate
3. 150 GHz FMAX with high drain breakdown voltage immunity by multi gate oxide dual work-function (MGO-DWF)-MO SFET
4. FinFET scaling to 10 nm gate length;yu;International Electron Devices Meeting Digest,0
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