Impact of technology scaling on the performance of domino CMOS logic-Reference-Cited by-同舟云学术

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Impact of technology scaling on the performance of domino CMOS logic

Published:2008-12 Issue: Volume: Page:
ISSN:
Container-title:2008 International Conference on Electronic Design
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Author:

Sharroush Sherif M.,Abdalla Yasser S.,Dessouki Ahmed A.,El-Badawy El-Sayed A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4781527/4786614/04786755.pdf?arnumber=4786755

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Effect of Noise Robustness on Domino Using Silicon Nano Materials;Silicon;2024-01-27

2. A variation resilient keeper design for high performance domino logic applications;Integration;2023-01

3. An efficient low power method for FinFET domino OR logic circuit;Microprocessors and Microsystems;2022-11

4. Impact of Silicon Stacked Transistors on Nano Scale Domino Logic;Silicon;2022-01-06

5. Domino Logic Keeper Circuit Design Techniques: A Review;Journal of The Institution of Engineers (India): Series B;2021-09-09

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