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Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs

  • Published:2016-05 Issue:5 Volume:24 Page:1636-1648
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Song Taigon,Liu Chang,Peng Yarui,Lim Sung Kyu

Funder

CISS through the MEST Global Frontier Project within the South Korean Government

National Science Foundation

Semiconductor Research Corporation

Intel Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effect of Power Supply Noise on Logical Reliability of MOS based Circuits;2023 Third International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2023-01-05

2. Wideband Analysis and Prolongation of Surrounding TGVs Shielding Structure in 3-D ICs;IEEE Microwave and Wireless Technology Letters;2023-01

3. Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays;IEEE Transactions on Reliability;2023

4. Systematic Design Considerations for Test Vehicle of TSV Ground Shielding Array;2022 23rd International Conference on Electronic Packaging Technology (ICEPT);2022-08-10

5. Multiobjective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3-D Integrated Chips;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-08
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