Author:
Zhao Peiyi,McNeely Jason,Golconda Pradeep,Bayoumi Magdy A.,Barcenas Robert A.,Kuang Weidong
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
42 articles.
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1. Review of Dual-Edge Triggered Low-Power D Flip-Flops;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29
2. The Application of MUX in the Realming of Domino Logic, Dynamic Consequently, and Transmission Gates: A Case Study with Performance Calculation;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19
3. Implementing Logical Shifters: For Funtionality Testing and Performance of Power Analysis;2023 3rd Asian Conference on Innovation in Technology (ASIANCON);2023-08-25
4. Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05
5. Low Power Explicit-Pulsed Single-Phase-Clocking Dual-edge-triggering Pulsed Latch Using Transmission Gate;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28