Low Power Explicit-Pulsed Single-Phase-Clocking Dual-edge-triggering Pulsed Latch Using Transmission Gate
Author:
Affiliation:
1. University of California, Irvine,Samueli School of Engineering,Irvine,CA,U.S
2. Chapman University,Fowler School of Engineering,Orange,CA,U.S
3. School of Science & Mathematics Mississippi College,Clinton,MS,U.S
Funder
Chapman University
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011378.pdf?arnumber=10011378
Reference15 articles.
1. An Ultra-Low-Voltage Single-Phase Adaptive Pulse Latch with Redundant Toggling Elimination
2. Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time
3. Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems
4. Design of Sequential Elements for Low Power Clocking System
5. Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches
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