Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse
Author:
Affiliation:
1. Department of Electrical Engineering, Indian Institute of Technology, Ropar, Rupnagar, India
Funder
SERB
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10164658/10113135.pdf?arnumber=10113135
Reference34 articles.
1. Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches
2. Memristor-Based Circuit Design for Multilayer Neural Networks
3. Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration
4. RRAM Device Models: A Comparative Analysis With Experimental Validation
5. Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing
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