Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage-Reference-Cited by-同舟云学术

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Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

Published:2011-10 Issue:10 Volume:19 Page:1911-1916
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ebrahimi Behzad,Rostami Masoud,Afzali-Kusha Ali,Pedram Massoud

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5978256/05546969.pdf?arnumber=5546969

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Development of a Method for Reducing the Power, Area and Delay Time for a Static Random Access Memory Cell;2022 International Conference on Electrical, Computer and Energy Technologies (ICECET);2022-07-20

2. A current model for FOI FinFETs with back-gate bias modulation;Solid-State Electronics;2021-11

3. Reliable and high performance asymmetric FinFET SRAM cell using back-gate control;Microelectronics Reliability;2020-01

4. Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays;IEEE Transactions on Circuits and Systems II: Express Briefs;2019-12

5. A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology;Journal of Computational Electronics;2019-03-28

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