Author:
Kuo Chun-Yi,Shih Chi-Jih,Lu Yi-Chang,Li James Chien-Mo,Chakrabarty Krishnendu
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
9 articles.
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1. Shallow trench isolation structure design for through‐silicon vias stress reduction;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2022-01-23
2. Defect Detection for 3D Through Silicon via Based on Machine Learning Approach;Nanoscience and Nanotechnology Letters;2017-08-01
3. Buffered Interconnects in 3D IC Layout Design;Proceedings of the 18th System Level Interconnect Prediction Workshop;2016-06-04
4. Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-03
5. Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone;IEEE Transactions on Components, Packaging and Manufacturing Technology;2015-08