An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs-Reference-Cited by-同舟云学术

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An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

Published:2004-06 Issue:6 Volume:12 Page:652-657
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Singh R.,Bhat N.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/28933/01302148.pdf?arnumber=1302148

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design;International Journal of Circuit Theory and Applications;2024-08-15

2. Compact Modeling and Design Exploration of Non-Destructive Read-Out 1T1C FeRAM;IEEE Transactions on Electron Devices;2024-08

3. Analyzing the Performance of a Low Power, High Performance Latch-Based Static Random-Access Memory Sense Amplifier for Epilepsy Detection;Journal of Nanoelectronics and Optoelectronics;2024-07-01

4. A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM;IEICE Electronics Express;2023-12-25

5. Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

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