THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration

Author:

Lu Jinming1ORCID,Huang Jian1,Wang Zhongfeng1ORCID

Affiliation:

1. School of Electronic Science and Engineering, Nanjing University, Nanjing, China

Funder

National Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Key Research Plan of Jiangsu Province of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. PBN: Progressive Batch Normalization for DNN Training on Edge Device;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

3. WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

4. Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

5. An FPGA-based Mix-grained Sparse Training Accelerator;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

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