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An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications

  • Published:2021-11 Issue:11 Volume:29 Page:1861-1874
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Emara Ahmed S.ORCID,Romanov DenisORCID,Roberts Gordon W.ORCID,Aouini SadokORCID,Ziabakhsh SoheylORCID,Parvizi Mahdi,Ben-Hamida NaimORCID

Funder

Mathematics of Information Technology and Complex Systems (MITACS) Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A stimulus identification method for high-resolution ADC linearity testing using low-precision ramp signals;IEICE Electronics Express;2024

2. A random shifting data weighted averaging algorithm for Nyquist-rate DAC;IEICE Electronics Express;2023-10-25

3. Detection of Catastrophic Faults in 6-Bit R-2R Ladder DAC;2023 8th International Conference on Electrical, Electronics and Information Engineering (ICEEIE);2023-09-28

4. High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis;2023 IEEE European Test Symposium (ETS);2023-05-22

5. Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01
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