Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares

Author:

Kim Jooyoung,Lee Woosung,Cho Keewon,Kang SunghoORCID

Funder

National Research Foundation of Korea (NRF) grand funded by the Korea government, Ministry of Science, ICT and Future Planning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. Efficient Built in Self Repair for Multiple RAMs;2023 IEEE 8th International Conference for Convergence in Technology (I2CT);2023-04-07

3. ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-06

4. TRUST: Through-Silicon Via Repair Using Switch Matrix Topology;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022

5. Memory test and repair technique for SoC based devices;IEICE Electronics Express;2021-04-25

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