Cost-Efficient SHA Hardware Accelerators

Author:

Chaves R.,Kuzmanov G.,Sousa L.,Vassiliadis S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 37 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. LiteHash: Hash Functions for Resource-Constrained Hardware;ACM Transactions on Embedded Computing Systems;2024-07-09

2. Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

3. Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices;Sensors;2022-11-25

4. High-performance Multi-function HMAC-SHA2 FPGA Implementation;2022 20th IEEE Interregional NEWCAS Conference (NEWCAS);2022-06-19

5. A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration;2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2022-05

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