Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs-Reference-Cited by-同舟云学术

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Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

Published:2006-04 Issue:4 Volume:14 Page:430-435
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kyeong-Sik Min ,Hun-Dae Choi ,Choi H.-Y.,Kawaguchi H.,Sakurai T.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/34317/01637473.pdf?arnumber=1637473

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3. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications;ACM Transactions on Embedded Computing Systems;2019-10-12

4. Clock gating methodologies and tools: a survey;International Journal of Circuit Theory and Applications;2015-06-15

5. Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-01

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