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Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks

  • Published:2010-01 Issue:1 Volume:18 Page:1-14
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ejlali Alireza,Al-Hashimi Bashir M.,Rosinger Paul,Miremadi Seyed Ghassem,Benini Luca

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-10

2. An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips;International Journal of Communication Networks and Distributed Systems;2020

3. Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip;IET Circuits, Devices & Systems;2019-12-20

4. A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs;2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2019-10

5. A Comparative Study on Automated Fault—Tolerant Route Discovery with Congestion Control Using TFRF Model for 3-D Network-on-Chips;Journal of Applied Security Research;2019-09-17
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