Segmented Architecture for Successive Approximation Analog-to-Digital Converters-Reference-Cited by-同舟云学术

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Segmented Architecture for Successive Approximation Analog-to-Digital Converters

Published:2014-03 Issue:3 Volume:22 Page:593-606
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Saberi Mehdi,Lotfi Reza

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/6746074/06490419.pdf?arnumber=6490419

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology;International Journal of Electronics and Telecommunications;2023-07-26

2. Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm;Chips;2023-02-27

3. A Low-Power Single-Path Bio-Impedance Measurement System Using an Analog-to-Digital Converter for I/Q Demodulation;IEEE Transactions on Biomedical Circuits and Systems;2022-12

4. A Dual Mode SAR ADC with Oversampling and Dithering for Extended Accuracy;2022 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia);2022-11-11

5. Enhancing the Accuracy and Speed of Sampling in Image Sensors by Designing Analog to Digital Converter with Power Decrease Approach;Journal of Sensors;2022-01-24

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