A Dual Mode SAR ADC with Oversampling and Dithering for Extended Accuracy
Author:
Affiliation:
1. School of Integrated Circuits, Tsinghua University,Beijing,China
2. Hesai Technology,Shanghai,China
3. CEC Huada Electronic Design Co., Ltd,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10103932/10103801/10103984.pdf?arnumber=10103984
Reference10 articles.
1. A 12-Bit Synchronous-SAR ADC for IoT Applications
2. A 10b 100MS/s l.13mW SAR ADC with binary-scaled error compensation;liu;2010 IEEE International Solid-State Circuits Conference - (ISSCC) ISSCC,0
3. An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC
4. A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals
5. A 12-bit 200-kS/s SAR ADC with hybrid RC DAC
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