Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS-Reference-Cited by-同舟云学术

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Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS

Published:2019-11 Issue:11 Volume:27 Page:2548-2555
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Na Taehui,Song Byungkyu,Choi Sara^ORCID,Kim Jung Pill,Kang Seung H.^ORCID,Jung Seong-Ook^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8880704/08765744.pdf?arnumber=8765744

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