Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches-Reference-Cited by-同舟云学术

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Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

Published:2018-10 Issue:10 Volume:26 Page:1881-1894
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Agarwal Sukarn^ORCID,Kapoor Hemangee K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8472222/08374980.pdf?arnumber=8374980

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27

2. CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches;ACM Transactions on Embedded Computing Systems;2022-01-14

3. ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache;2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP);2021-07

4. DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches;2021 22nd International Symposium on Quality Electronic Design (ISQED);2021-04-07

5. Improving the Performance of Hybrid Caches Using Partitioned Victim Caching;ACM Transactions on Embedded Computing Systems;2021-01-31

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