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Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

  • Published:2020-09 Issue:9 Volume:28 Page:2028-2041
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ranasinghe Anuradha ChathurangaORCID,Gerez Sabih H.ORCID

Funder

Dutch NWO Applied and Engineering Sciences program ZERO: Towards Energy Autonomous Systems for IoT

Dialog Semiconductor B.V., The Netherlands

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

2. GOMARL: Global Optimization of Multiplier using Multi-Agent Reinforcement Learning;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications;Tehnicki vjesnik - Technical Gazette;2024-02-15

4. A Nonlinear Function Logic Computing Architecture With Low Switching Activity;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-09

5. Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators;Journal of Computer Science and Technology;2023-03-30
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