Design of high speed CRC algorithm for ethernet on FPGA using reduced lookup table algorithm

Author:

Bajarangbali ,Anand P. Aparna

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Genetic Programming approach for hardware-oriented hash functions for network security applications;Applied Soft Computing;2024-11

2. A Formal Design of Parallel CRC Circuit;2023 5th International Conference on Electronic Engineering and Informatics (EEI);2023-06-30

3. A Method of High-speed Parallel CRC Computation;2023 5th International Conference on Electronic Engineering and Informatics (EEI);2023-06-30

4. Design and implementation of parallel CRC algorithm for fibre channel on FPGA;The Journal of Engineering;2019-10-10

5. Effective FPGA Architecture for General CRC;Architecture of Computing Systems – ARCS 2019;2019

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