Author:
Tomar V. K.,Sachdeva Ashish
Cited by
8 articles.
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1. SRAM Cell Leakage Reduction Methodologies for Low Leakage Cache Memories;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
2. Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
3. Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits;Micromachines;2023-02-28
4. Performance Analysis of Various CMOS SRAM Cells;2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT);2022-10-03
5. Design of Low Power PMOS Biased Sense Amplifier Using Lector Approach;2022 8th International Conference on Smart Structures and Systems (ICSSS);2022-04-21