Customization of a Deep Learning Accelerator-Reference-Cited by-同舟云学术

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Customization of a Deep Learning Accelerator

Published:2019-04 Issue: Volume: Page:
ISSN:
Container-title:2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
language:
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Author:

Luo Shien-Chun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8734473/8741402/08741855.pdf?arnumber=8741855

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CRSM: Computation Reloading Driven by Spatial-Temporal Mobility in Edge-Assisted Automated Industrial Cyber-Physical Systems;IEEE Transactions on Industrial Informatics;2022-12

2. Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study;2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS);2022-04-06

3. ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design;2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2021-04-19

4. Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform;VLSI-SoC: Design Trends;2021

5. Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator;2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC);2020-10-05

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