A Reconfigurable DT $\Delta \Sigma $ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers

Author:

Bettini Luca,Christen Thomas,Burger Thomas,Huang Qiuting

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Dual-Mode Continuous–Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09

2. A 1.2 V, 80–230 MHz, 1.75 mW Phase Locked Loop N- Integer Clock Synthesizer;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28

3. The design of ΔΣ-ADC in MEMS gyro interface ASIC;Microelectronics Journal;2023-04

4. Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters;Analog Integrated Circuits and Signal Processing;2021-08-25

5. Modeling of Reconfigurable ΣΔ Modulator for Multi-standard Wireless Receivers in Verilog-A;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23

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