AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration-Reference-Cited by-同舟云学术

AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration

Published:2023-03 Issue:1 Volume:13 Page:225-236
ISSN:2156-3357
Container-title:IEEE Journal on Emerging and Selected Topics in Circuits and Systems
language:
Short-container-title:IEEE J. Emerg. Sel. Topics Circuits Syst.

Author:

Tabrizchi Sepehr¹^ORCID,Nezhadi Ali¹^ORCID,Angizi Shaahin²^ORCID,Roohi Arman¹^ORCID

Affiliation:

1. School of Computing, University of Nebraska–Lincoln, Lincoln, NE, USA

2. Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, USA

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/5503868/10078357/10036067-aam.pdf

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5. A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications

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1. PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

2. PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems;IEEE Transactions on Emerging Topics in Computing;2023-10

3. Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07

4. Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

5. SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05