Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study

Author:

Kochar Nakul1ORCID,Ekiert Lucas1ORCID,Najafi Deniz1ORCID,Fan Deliang2ORCID,Angizi Shaahin1ORCID

Affiliation:

1. New Jersey Institute of Technology, Newark, NJ, USA

2. Arizona State University, Tempe, AZ, USA

Funder

National Science Foundation

Publisher

ACM

Reference39 articles.

1. MR-PIPA: An Integrated Multilevel RRAM (HfO x )-Based Processing-In-Pixel Accelerator

2. AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration

3. S. Zhou , Y. Wu , Z. Ni , X. Zhou , H. Wen , and Y. Zou , ?Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients," arXiv preprint arXiv:1606.06160 , 2016 . S. Zhou, Y. Wu, Z. Ni, X. Zhou, H. Wen, and Y. Zou, ?Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients," arXiv preprint arXiv:1606.06160, 2016.

4. C. Eckert , X. Wang , J. Wang , A. Subramaniyan , R. Iyer , D. Sylvester , D. Blaaauw , and R. Das , ?Neural cache: Bit-serial in-cache acceleration of deep neural networks," in 2018 ACM/IEEE 45Th annual international symposium on computer architecture (ISCA) . IEEE , 2018 , pp. 383 -- 396 . C. Eckert, X. Wang, J. Wang, A. Subramaniyan, R. Iyer, D. Sylvester, D. Blaaauw, and R. Das, ?Neural cache: Bit-serial in-cache acceleration of deep neural networks," in 2018 ACM/IEEE 45Th annual international symposium on computer architecture (ISCA). IEEE, 2018, pp. 383--396.

5. S. Angizi , Z. He , A. S. Rakin , and D. Fan , ?Cmp-pim: an energy-efficient comparator-based processing-in-memory neural network accelerator," in Proceedings of the 55th Annual Design Automation Conference , 2018 , pp. 1 -- 6 . S. Angizi, Z. He, A. S. Rakin, and D. Fan, ?Cmp-pim: an energy-efficient comparator-based processing-in-memory neural network accelerator," in Proceedings of the 55th Annual Design Automation Conference, 2018, pp. 1--6.

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