A Common-Mode Voltage Elimination Method With Active Neutral Point Voltage Balancing Control for Three-Level T-Type Inverter
Author:
Affiliation:
1. Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan
Funder
Ministry of Science and Technology, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Control and Systems Engineering
Link
http://xplorestaging.ieee.org/ielx7/28/9956958/09865175.pdf?arnumber=9865175
Reference30 articles.
1. Improved common-mode voltage elimination modulation with dead-time compensation for three-level neutral-point-clamped three-phase inverters
2. Analysis and realization of a pulsewidth modulator based on voltage space vectors
3. Modified DC-Bus Voltage Balancing Algorithm for a Three-Level Neutral-Point-Clamped PMSM Inverter Drive With Reduced Common-Mode Voltage
4. Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance Scheme for the Quasi-Z-Source Three-Level T-Type Inverter
5. A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive
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