Improved common-mode voltage elimination modulation with dead-time compensation for three-level neutral-point-clamped three-phase inverters
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6624149/6646663/06647266.pdf?arnumber=6647266
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Impact of Dead Time Effect on Common Mode Electromagnetic Interference in PMSM Drives;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20
2. Optimal Pulse Width Modulation of Three-Level Converters With Reduced Common-Mode Voltage;IEEE Transactions on Industry Applications;2024-05
3. EMI Modeling Method and Active Suppression Technology of Common-Mode Electromagnetic Interference in Three-Phase Two-Level Inverter Based on Four-Bridge Topology;IEEE Transactions on Industry Applications;2024-05
4. Hardware software co-simulation of a digital EMI filter using Xilinx system generator;Archives of Electrical Engineering;2024-01-02
5. A Common-Mode Voltage Elimination Method With Active Neutral Point Voltage Balancing Control for Three-Level T-Type Inverter;IEEE Transactions on Industry Applications;2022-11
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