A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9060424/9075871/09075885.pdf?arnumber=9075885
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
2. A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06
3. A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02
4. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04
5. A 56-GHz Fractional-N PLL With 110-fs Jitter;IEEE Journal of Solid-State Circuits;2023-01
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