A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS-Reference-Cited by-同舟云学术

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A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS

Published:2021-04 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Mokhtar Mohamed A.,Abdelaal Ahmed,Sporer Markus,Becker Joachim,Kauffman John G.,Ortmanns Maurits

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9431363/9431390/09431391.pdf?arnumber=9431391

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel 16-bit ADC Based on Third-order Σ-∆ Modulator with Zero Optimization;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

2. A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

3. Weightings in Incremental ADCs: A Tutorial Review;2023 IEEE Custom Integrated Circuits Conference (CICC);2023-04

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