A Novel 16-bit ADC Based on Third-order Σ-∆ Modulator with Zero Optimization
Author:
Affiliation:
1. Chang’an University,School of Electronics and Control Engineering,Xi’an,China
Funder
Research and Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396379.pdf?arnumber=10396379
Reference5 articles.
1. A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS
2. A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction
3. A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC for X-ray sensor array
4. High-Resolution ADCs for Biomedical Imaging Systems
5. A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques
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