A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9431363/9431390/09431559.pdf?arnumber=9431559
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. Comprehensive TCAD-Based Retention Study of Thyristor RAM (TRAM) for Low-Power and High-Speed Cryogenic Memory Applications;IEEE Transactions on Electron Devices;2024-02
3. Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2023-12
4. The Future is Frozen: Cryogenic CMOS for High-Performance Computing (Invited);Chip;2023-12
5. Cryogenic CMOS as an Enabler for Low Power Dynamic Logic;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07
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