A 0.6V Programmable Frequency Divider and Digitally Controlled Oscillator for use in a Digital PLL in the Subthreshold Region
Author:
Funder
Center of Innovation Program (COI)
Japan Science and Technology Agency (JST)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9294155/9294779/09294810.pdf?arnumber=9294810
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A 0.6V Beat-Frequency ADC with Processing of Oscillator Internal States for Resolution Improvement;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
3. Variable Duty Cycle Pulse Generation for Low Complexity Randomization in Machine Learning;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
4. Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28
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