A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR

Author:

Samanta Smrutilekha,Sarkar Santanu

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Low Power Current Steering DAC Using 45nm CMOS Technology;2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2024-04-26

2. A 12-bits 100 MSPS Current-Steering DAC With Low-Power In 40nm CMOS;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. Dynamic Switching Compensation Technique Mitigating Code-Dependent Switching Distortion in CS-DACs;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24

4. A Flash-based Digital to Analog Converter for Low Power Applications;2022 IEEE 40th International Conference on Computer Design (ICCD);2022-10

5. Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications;International Journal of Software Science and Computational Intelligence;2022-07-18

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