Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor-Reference-Cited by-同舟云学术

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Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Published:2013-11 Issue: Volume: Page:
ISSN:
Container-title:IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society
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Author:

Gomez-Cornejo Julen,Zuloaga Aitzol,Kretzschmar Uli,Bidarte Unai,Jimenez Jaime

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6683943/6699103/06699483.pdf?arnumber=6699483

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V;Microelectronics Reliability;2021-05

2. A Fault-Tolerant Time-Predictable Processor;2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC);2019-10

3. Lockstep Dual-Core ARM A9: Implementation and Resilience Analysis Under Heavy Ion-Induced Soft Errors;IEEE Transactions on Nuclear Science;2018-08

4. A novel BRAM content accessing and processing method based on FPGA configuration bitstream;Microprocessors and Microsystems;2017-03

5. Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications;Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17;2017

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