Wafer-scale Fabrication of Vertical GaN p-n Diodes with Graded JTE Structures Using Multiple-zone Boron Implantation

Author:

Miura Yoshinao1,Hirai Hirohisa1,Nakajima Akira1,Harada Shinsuke1

Affiliation:

1. National Institute of Advanced Industrial Science and Technology,Advanced Power Electronics Research Center,Tsukuba, Ibaraki,Japan

Publisher

IEEE

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Boron-Implanted Termination Structures for Vertical GaN Power Devices with Highly Enhanced Breakdown Voltage;IEEJ Transactions on Electronics, Information and Systems;2024-03-01

2. 1.2-kV Vertical GaN PIN Rectifier With Ion-Implanted Floating Guard Rings;IEEE Transactions on Electron Devices;2023-09

3. A Novel Junction Termination Technique with Excellent Cost-Performance and Extraordinary Anti-Charge-Deviation Ability;2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2023-05-28

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