Dose Effects on Bipolar Transistors Belonging to a CMOS SOI Process
Author:
Affiliation:
1. Université de Montpellier, IES - UMR UM/CNRS 5214, 860 Rue de St Priest, Montpellier, France and Delphea,Montpellier,France
2. Université de Montpellier, IES - UMR UM/CNRS 5214, 860 Rue de St Priest,Montpellier,France
3. MICROCHIP,Nantes,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10412245/10412349/10412607.pdf?arnumber=10412607
Reference14 articles.
1. Elimination of Single Event Latch-Up in the ATMEL ATMX150RHA Rad-Hard CMOS 150nm Cell-Based ASIC Family
2. Single Event Dielectric Rupture Characterization of Microchip High Voltage Devices
3. Analysis of Total Dose Effects on a PDSOI n-channel High Voltage Transistor for Analog Applications;Perez
4. Total Ionizing Dose Effect in LDMOS Oxides and Devices
5. Gate Grounded n-MOS Sensibility to Ionizing Dose
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