TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system
-
Published:2021
Issue:6
Volume:18
Page:9050-9075
-
ISSN:1551-0018
-
Container-title:Mathematical Biosciences and Engineering
-
language:
-
Short-container-title:MBE
Author:
Zhao Yongjie, ,Li Sida,Huang Zhiping
Abstract
<abstract>
<p>This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.</p>
</abstract>
Publisher
American Institute of Mathematical Sciences (AIMS)
Subject
Applied Mathematics,Computational Mathematics,General Agricultural and Biological Sciences,Modelling and Simulation,General Medicine
Reference34 articles.
1. M. I. Zahoor, Z. Dou, S. B. H. Shah, I. U. Khan, S. Ayub, T. R. Gadekallu, Pilot decontamination using asynchronous fractional pilot scheduling in massive MIMO systems, Sensors, 20 (2020), 6213. 2. M. H. Abidi, H. Alkhalefah, K. Moiduddin, M. Alazab, M. K. Mohammed, W. Ameen, et al., Optimal 5G network slicing using machine learning and deep learning concepts, Comput. Stand. Interfaces, 76 (2021), 103518. 3. N. Ning, Z. Sui, J. Li, S. Wu, H. Chen, S. Xu, et al., Multi scaling coefficients technique for noisy signal based gain error background calibration, in 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), (2012), 1–2. 4. N. Ning, Z. Sui, J. Li, S. Wu, H. Chen, S. Xu, et al., Multiscaling coefficients technique for gain error background calibration in pipelined ADC, J. Circuits Syst. Comput., 23 (2014), 1450034. 5. C. C. Hsu, F. C. Huang, C. Y. Shih, C. C. Huang, Y. H. Lin, C. C. Lee, et al., An 11b 800MS/s time-interleaved ADC with digital background calibration, in 2007 IEEE International Solid-State Circuits Conference, (2017), 464–615.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|