Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

Author:

Mahapatra Nihar R.,Dutt Shantanu

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference14 articles.

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2. J. Bruck, R. Cypher, and C.-T. Ho, Fault-tolerant meshes with small degree, in Proc ACM Symp. Parallel Algorithms and Architectures, 1993, pp. 1–10.

3. The full-use-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays;Chean;IEEE Trans. Comput.,1990

4. F. R. K. Chung, F. T. Leighton, and A. L. Rosenberg, Diogenes: A methodology for designing fault-tolerant VLSI processor arrays, in Proc. Thirteenth Fault Tolerant Comput. Symp., June 1983, pp. 26–31.

5. Some practical issues in the design of fault-tolerant multiprocessors;Dutt;IEEE Trans. Comput.,1992

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