High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA

Abstract

In this paper, systolic array-based novel architecture for dual-tree complex wavelet transform (DTCWT) computation is designed and implemented on FPGA. The wavelet filter coefficients of DTCWT are quantized and rounded to nearest integer and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx Virtex II FPGA. For 2D implementation, the design operates at a maximum frequency of 156[Formula: see text]MHz and consumes power less than 3[Formula: see text]W. This is the first design with systolic array architecture on FPGA for DTCWT computation operating at frequencies greater than 100[Formula: see text]MHz.