A NEW APPROACH TO CHARACTERIZE AND PREDICT LIFETIME OF DEEP-SUBMICRON NMOS DEVICES

Abstract

Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep submicron (< 0.25 μm) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices.