New Realization and Implementation of Fixed-Point IIR Digital Filters

Author:

Tawfik A.1,El-Guibaly F.1,Agathoklis P.1

Affiliation:

1. Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055 Victoria, B.C., Canada V8W 3P6, Canada

Abstract

A new low-roundoff noise realization for narrow-band IIR digital filters with residue feedback and a block triangular system matrix is presented. The block triangular form of the system matrix allows a reduction in the number of arithmetic operations required for the implementation and leads also to a realization which is suitable for high speed implementation. Numerical comparison between the proposed structure and three other low-noise structures shows that the proposed structure provides excellent performance in terms of output roundoff noise and coefficient sensitivity. The output roundoff noise is slightly higher than that of the optimal residue feedback realization proposed by Williamson9 but lower than the optimal realization without residue feedback proposed by Mullis, Roberts and Hwang.6,7 Further an efficient (in terms of speed) VLSI processor array implementation of the proposed IIR structure is also presented. The proposed implementation has been obtained by taking advantage of both the parallel feature of the residue feedback and the block triangular structure of the system matrix of the proposed realization. A hardware comparison between the proposed implementation and another implementation which is based on direct form shows that the proposed implementation provides a higher sampling rate for any narrow-band filter.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-02

2. Overflow handling in inner-product processors;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2000

3. A fast parallel multiplier-accumulator using the modified Booth algorithm;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2000

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